A Method for Error Detection and Correction of Fault Secure OLS Decoder

Reliability is one of the major issues of advanced electronic circuits. In recent years there are several error correction codes (ECC) developed to protect the memories and registers in electronic circuits. But the encoder and decoder circuit may also suffer errors, for these reasons concurrent error detection (CED) and correction technique for orthogonal Latin square (OLS) decoder is proposed. This technique is strongly fault secured for single stuck at faults. The most significant advantage is that it achieves 100 percentage fault coverage for the whole CED circuit. The CED and correction is applicable to both binary and non binary OLS codes also. The proposed method can be achieved by performing the checking in parallel with the majority voting, syndrome generator and error corrector and orthogonal generator in the case of the decoder. Synthesis can be done in Xilinx ISE design suite 13.2 and simulation can be done with ModelSim.